1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a structure and a planarizing method in an insulating layer of a semiconductor device by which insulating layers made of organic and inorganic substances are aligned on the same plane and the insulating layers are planarized by reducing a step coverage.
2. Description of the Prior Art
Recently, a chip size of a semiconductor circuit is in a tendency of increasing, thus, a switching speed of the circuit has much influence on a transmitting speed of wiring. For instance, assuming that a resistance of the wiring is R and a capacitance of an insulating layer is C, the chip speed becomes low due to a "R.C" time delay effect.
Therefore, a study for improving the "R.C" time delay is proceeding by adapting a low resistance wiring substance such as Cu instead of an aluminum for an insulating layer, and an organic polymer having a dielectric constant such as a benzocyclobutene(BCD) polymer or a fluorinated polyimide instead of a silicon oxide film. However, since the organic polymer has a higher thermal expansion coefficient than the inorganic substance, it is easily deformed during a thermal process and mechanical strength thereof is degraded.
Additionally, as the semiconductor circuit is integrated, a topology in a structure of a lower part of the wiring in the memory device is increased, for which a method for planarizing the insulating layer is required in order to obtain margins of an alignment accuracy and a depth of focus in lithography process for forming a contact hole or a conductor line.